Energy Savings with Appropriate Interconnection Networks in Parallel DSP
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چکیده
This paper presents an instruction level power model for a very long instructions word (VLIW) single instruction multiple data (SIMD) digital signal processor (DSP). We show that power consuming memory accesses can be reduced in such SIMD processor architectures with an appropriate network connecting the parallel register files and/or data paths. Several network topologies are analyzed for a variety of digital signal processor algorithms concerning energy issues.
منابع مشابه
Using the Multistage Cube Network Topology in Parallel Supercomputers. in Interconnection Networks for Large-scale Parallel Processing
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تاریخ انتشار 2002